Repositories | Md Zesun Ahmed Mia

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Choose a practical starting point

Follow the tutorials, browse featured project stories, or open the portfolio getting-started guide.

Each code project keeps its own repository. Labels distinguish usable tools, measured experiments, learning exercises, architecture drafts, and roadmap-only projects. The Rust entry contains public curriculum metadata; its basics remain private.

Hardware agent tooling

hw-agent-tooling

Usable tool

Find and choose the hardware-agent tools in this portfolio.

First task: Follow the small FIFO walkthrough to see RTL review, simulation, and synthesis together.

Scope: A documentation hub with example transcripts; each tool is installed and maintained in its own repository.

FIFO walkthrough · Project story

eda-docker-images

Usable tool

Run open-source hardware tools in shared Docker or Podman images.

First task: Pull the Verilog image and run the counter fixture using the Quickstart.

Scope: Four EDA image definitions and smoke fixtures. Tool availability depends on the selected image and tag.

Image Quickstart

eda-devcontainer

Usable tool

Develop hardware projects in editor containers backed by EDA images.

First task: Open the Verilog profile in a development container and run its fixture checks.

Scope: Development environments for four domains. A Docker or Podman runtime and the corresponding base image are required.

Devcontainer Quickstart

mcp-verilog

Usable tool

Lint, compile, and simulate Verilog/SystemVerilog through an MCP server.

First task: Configure the server in your MCP client, then call verilog_toolchain_info before running a design.

Scope: Published MCP server. The npx command starts a stdio server that waits for a client; EDA execution also needs its documented host/container tools.

Runtime requirements and configuration

hw-agent-skills

Usable tool

Apply hardware-review and verification rubrics through coding-agent instruction files.

First task: Read the RTL reviewer rubric, then apply it to a clocked Verilog block.

Scope: Eight instruction/rubric packs. These guide review behavior; executing EDA commands requires separate tools.

RTL review rubric

hw-verification-suite

Usable tool

Reuse Python testbench components for LIF neuron tiles and AER routing.

First task: Inspect the LIF scoreboard and compare its expected membrane state with your design.

Scope: Python verification components for specific interfaces. Adapting them to another design requires matching its signals and timing; quick checks skip simulation.

LIF scoreboard

mcp-cocotb

Usable tool

Run Python hardware testbenches and inspect their results through an MCP server.

First task: Configure the server in your MCP client, then call cocotb_toolchain_info before running a design.

Scope: Published MCP server. The npx command starts a stdio server that waits for a client; EDA execution also needs its documented host/container tools.

Runtime requirements and configuration

mcp-yosys

Usable tool

Inspect synthesis, hierarchy, and unintended latches before physical design through an MCP server.

First task: Configure the server in your MCP client, then call yosys_toolchain_info before running a design.

Scope: Published MCP server. The npx command starts a stdio server that waits for a client; EDA execution also needs its documented host/container tools.

Runtime requirements and configuration

mcp-rtl-review

Usable tool

Review RTL assignment, width, and reset rules before simulation through an MCP server.

First task: Configure the server in your MCP client, then call rtl_toolchain_info before running a design.

Scope: Published static-analysis server using a Verilator AST backend. A review score covers the implemented rules and does not replace simulation or formal properties. The npx command waits for an MCP client.

Runtime requirements and configuration

mcp-openroad

Usable tool

Run physical-design stages and inspect timing for a netlist through an MCP server.

First task: Configure the server in your MCP client, then call openroad_toolchain_info before running a design.

Scope: Published MCP server. The npx command starts a stdio server that waits for a client; EDA execution also needs its documented host/container tools.

Runtime requirements and configuration

mcp-gds

Usable tool

Inspect layouts, stream out GDS, and run geometry or netlist checks through an MCP server.

First task: Configure the server in your MCP client, then call gds_toolchain_info before running a design.

Scope: Published MCP server for layout and netlist checks. Smoke geometry checks use the selected deck; PDK-specific extraction/LVS requires appropriate technology and setup files. The npx command waits for an MCP client.

Runtime requirements and configuration

mcp-formal

Usable tool

Check assertions and run bounded or inductive RTL proofs through an MCP server.

First task: Configure the server in your MCP client, then call formal_toolchain_info before running a design.

Scope: Published MCP server with explicit proof outcomes. A proof applies to the supplied properties, assumptions, engine, and bounds; unknown or timeout is not success. The npx command waits for an MCP client.

Runtime requirements and configuration

mcp-fpga

Usable tool

Synthesize and route FPGA designs and prepare bitstreams through an MCP server.

First task: Configure the server in your MCP client, then call fpga_toolchain_info before running a design.

Scope: Published MCP server for iCE40/ECP5 flows. Programming defaults to a dry run and requires an attached board for an actual hardware check. The npx command waits for an MCP client.

Runtime requirements and configuration

mcp-spice

Usable tool

Run ngspice circuit netlists and retrieve measurement results through an MCP server.

First task: Configure the server in your MCP client, then call spice_toolchain_info before running a design.

Scope: Published MCP server. The npx command starts a stdio server that waits for a client; EDA execution also needs its documented host/container tools.

Runtime requirements and configuration

hw-agent-scaffold

Usable tool

Create a starter RTL project and configuration for nine hardware MCP servers.

First task: Run npx @zesun33/create-hw-agent my-asic, inspect the generated files, then follow its README.

Scope: Scaffolding is available from npm. Simulation and physical design still need a container runtime, images, and any relevant PDK.

Generated project instructions · Project story

gh-actions-for-hw

Usable tool

Run hardware checks through reusable GitHub Actions.

First task: Copy the Verilog simulation action usage into a workflow for your RTL and testbench.

Scope: Six composite actions backed by container images. Simulation, synthesis, and physical-design checks have different inputs and prerequisites.

Workflow usage

kernel-forge

Usable tool

Generate CUDA kernel templates and inspect correctness, timing, and modeled Roofline limits.

First task: Install from the checkout and run forge doctor --json before generating a kernel.

Scope: A Python CLI with CUDA templates and modeled Roofline analysis. Actual execution requires a CUDA GPU/toolkit; modeled limits are separate from measured timings.

CLI Quickstart · Project story

agentic-asic

Usable tool

Coordinate RTL review, verification, synthesis, and implementation through EDA MCP servers.

First task: Install the CLI from the checkout, run asic doctor, then inspect the counter demo.

Scope: An orchestrator over the MCP servers. Results apply to the selected design, constraints, tools, and PDK; a successful run does not establish manufacturing qualification.

CLI walkthrough · Project story

ML systems

cuda-gemm-optimization

Measured experiment

Compare correctness and measured FP32 throughput across naive, tiled, and cuBLAS GEMM.

First task: Read the recorded comparison, then run the checked GEMM executable on your own selected GPU.

Scope: Implemented CUDA comparison with recorded RTX A5000 measurements. Speedups depend on shape and hardware; later optimizations remain future work.

Benchmark method and limitations · Project story

cuda-memory-benchmark

Learning exercise

Learn CUDA memory behavior through notes and a bandwidth exercise scaffold.

First task: Read the memory-hierarchy notes, then implement the TODOs in the global-memory exercise.

Scope: Notes and an incomplete CUDA exercise are present. Timing, allocation, and copy-kernel TODOs must be completed before it provides a bandwidth result.

Memory-hierarchy notes

parallel-computing-lab

Learning exercise

Learn CPU parallelism by completing OpenMP exercises.

First task: Read the OpenMP notes and uncomment the first exercise one section at a time.

Scope: Two OpenMP exercises with commented-out parallel sections. Reductions, synchronization, MPI, and measured scaling studies are future work.

OpenMP basics

resnet-tensorrt-bench

Roadmap

Plan a future ResNet inference study comparing precision, latency, and accuracy.

First task: Review the planned export, calibration, and comparison stages before choosing the first implementation.

Scope: Planning documents only. Model export, engines, datasets, accuracy checks, and benchmark code are not implemented here yet.

Planned implementation stages

triton-flash-attention-lite

Roadmap

Plan a future tiled-attention implementation and correctness/performance study.

First task: Read the roadmap and define a reference attention calculation before implementing a Triton kernel.

Scope: Planning documents only; no attention kernel or measured benchmark is present.

Planned attention study

Silicon designs

lif-spiking-core

Implemented RTL; partial coverage

Study and simulate LIF neuron tiles, AER routing, and a 2x2 neuromorphic mesh.

First task: Read the architecture, then follow the neuron/tile testbench paths and verification notes.

Scope: Implemented RTL and testbenches with historical results. Coverage is partial; implementation artifacts and timing estimates are not measurements of fabricated silicon.

Architecture overview · Project story

cim-bit-serial-pe

Architecture draft

Specify a proposed bit-serial compute-in-memory processing element.

First task: Work through the activation-bit accumulation equation and the proposed interface.

Scope: Architecture draft only: no RTL, simulation tests, measured area, or power results are present.

Arithmetic and interface proposal

neuro-cim-tile

Architecture draft

Specify a proposed compute-in-memory tile and its digital/device-model boundaries.

First task: Trace the proposed row-driver, crossbar, accumulator, and activation interfaces.

Scope: Architecture draft only. RTL, behavioral device models, calibration data, and verification are future work.

Tile hierarchy proposal

tiny-tpu-systolic-array

Architecture draft

Specify a proposed INT8 systolic-array dataflow and interface.

First task: Trace one small matrix product through the proposed skewed input schedule.

Scope: Architecture draft only: no synthesizable array, executable regression, or measured implementation is present.

Systolic dataflow proposal

Practical tutorials

hw-ml-tutorials

Guided examples

Learn practical hardware and GPU workflows with step-by-step tutorials and runnable examples.

First task: Run the event-counter positive and negative tests, then follow the MCP workflow lesson.

Scope: Eight lessons and runnable hardware fixtures, a university resource library, a Windows setup guide, and an initial GCD course specification. The new ASIC course implementations are upcoming work; GPU measurements require actual CUDA hardware.

First simulation tutorial

Rust systems

rust-systems-track

Curriculum metadata; basics private

Follow private Rust fundamentals toward planned GEMM and LIF/AER systems projects.

First task: Use the plan and tracker to understand the sequence and phase exit criteria.

Scope: Basics remain private. The public systems bridge and golden-model repositories are future phases, not released tools.

Curriculum and exit criteria

Website source

This academic website uses Jekyll and the al-folio theme. The portfolio catalog supplies the descriptions and scope used in this directory.