LIF spiking core: from neuron to mesh
Study event-driven neuron tiles and routing with reference models, simulation tests, and coverage notes.
The problem
A neuromorphic hardware design combines fixed-point neuron dynamics, synaptic configuration, pipeline timing, and spike routing. Checking only a neuron equation leaves interface and scheduling behavior untested.
What I built
I built neuron and tile RTL, a five-port AER router, and an integrated 2×2 mesh, with Python reference models and simulation testbenches. The repository preserves open-tool implementation artifacts and their evidence limits.
Implemented RTL; partial coverage
Who it is for: RTL and neuromorphic-computing developers studying event-driven neuron tiles and routing.
First task: Read the architecture, then follow the neuron/tile testbench paths and verification notes.
What you can produce: LIF neuron/tile/router RTL, reference models, simulation tests, and recorded implementation artifacts.
Current scope: Implemented RTL and testbenches with historical results. Coverage is partial; implementation artifacts and timing estimates are not measurements of fabricated silicon.
Start with the example Source and documentation Step-by-step tutorials
A first useful result
The tutorial programs one synapse and traces input pipelining, threshold crossing, subtractive reset, and refractory suppression in Python. It then points to the RTL comparison testbench. The model trace is an accessible first step without a simulator.
Evidence and limits
Verification notes distinguish recorded passes from partial functional coverage. A model trace establishes software behavior; hardware changes need fresh RTL tests. Open-tool artifacts do not establish fabricated silicon, complete timing signoff, or calibrated physical-device behavior.